svcadm(1M)을 검색하려면 섹션에서 1M 을 선택하고, 맨 페이지 이름에 svcadm을 입력하고 검색을 누른다.
isalist(7)
Standards, Environments, Macros, Character Sets, and miscellany
isalist(7)
NAME
isalist - the native instruction sets known to Solaris software
DESCRIPTION
The possible instruction set names returned by isalist(1) and the
SI_ISALIST command of sysinfo(2) are listed here.
The list is ordered within an instruction set family in the sense that
later names are generally faster then earlier names; note that this is
in the reverse order than listed by isalist(1) and sysinfo(2). In the
following list of values, numbered entries generally represent increas‐
ing performance; lettered entries are either mutually exclusive or can‐
not be ordered.
This feature is obsolete and may be removed in a future version of
Solaris. The lists below do not reflect all the extensions that have
been made by modern processors. See isainfo(1) and getisax(2) for bet‐
ter ways to handle instruction set extensions.
SPARC Platforms
Where appropriate, correspondence with a given value of the -xarch
option of Oracle Developer Studio C compiler is indicated. Other com‐
pilers might have similar options.
1a. sparc
Indicates the SPARC V8 instruction set, as defined in The SPARC
Architecture Manual, Version 8, Prentice-Hall, Inc., 1992. Some
instructions (such as integer multiply and divide, FSMULD, and all
floating point operations on quad operands) can be emulated by the
kernel on certain systems.
1b. sparcv7
Same as sparc. This corresponds to code produced with the -xarch=v7
option of the Oracle Developer Studio C compiler.
2. sparcv8-fsmuld
Like sparc, except that integer multiply and divide must be exe‐
cuted in hardware. This corresponds to code produced with the
-xarch=v8a option of the Oracle Developer Studio C compiler.
3. sparcv8
Like sparcv8-fsmuld, except that FSMULD must also be executed in
hardware. This corresponds to code produced with the -xarch=v8
option of the Oracle Developer Studio C compiler.
4. sparcv8plus
Indicates the SPARC V8 instruction set plus those instructions in
the SPARC V9 instruction set, as defined in The SPARC Architecture
Manual, Version 9, Prentice-Hall, 1994, that can be used according
to The V8+ Technical Specification. This corresponds to code pro‐
duced with the -xarch=v8plus option of the Oracle Developer Studio
C compiler.
5a. sparcv8plus+vis
Like sparcv8plus, with the addition of those UltraSPARC I Visual‐
ization Instructions that can be used according to The V8+ Techni‐
cal Specification. This corresponds to code produced with the
-xarch=v8plusa option of the Oracle Developer Studio C compiler.
5b. sparcv8plus+fmuladd
Like sparcv8plus, with the addition of the Fujitsu SPARC64 floating
multiply-add and multiply-subtract instructions.
6. sparcv9
Indicates the SPARC V9 instruction set, as defined in The SPARC
Architecture Manual, Version 9, Prentice-Hall, 1994.
7a. sparcv9+vis
Like sparcv9, with the addition of the UltraSPARC I Visualization
Instructions.
7b. sparcv9+vis2
Like sparcv9, with the addition of the UltraSPARC III Visualization
Instructions.
7c. sparcv9+fmuladd
Like sparcv9, with the addition of the Fujitsu SPARC64 floating
multiply-add and multiply-subtract instructions.
x86 Platforms
1. i386
The Intel 80386 instruction set, as described in The i386 Micropro‐
cessor Programmer's Reference Manual.
2. i486
The Intel 80486 instruction set, as described in The i486 Micropro‐
cessor Programmer's Reference Manual. (This is effectively i386,
plus the CMPXCHG, BSWAP, and XADD instructions.)
3. pentium
The Intel Pentium instruction set, as described in The Pentium Pro‐
cessor User's Manual. (This is effectively i486, plus the CPU_ID
instruction, and any features that the CPU_ID instruction indicates
are present.)
4. pentium+mmx
Like pentium, with the MMX instructions guaranteed present.
5. pentium_pro
The Intel PentiumPro instruction set, as described in The Pen‐
tiumPro Family Developer's Manual. (This is effectively pentium,
with the CMOVcc, FCMOVcc, FCOMI, and RDPMC instructions guaranteed
present.)
6. pentium_pro+mmx
Like pentium_pro, with the MMX instructions guaranteed present.
7. amd64
The AMD Opteron instruction set, as described in the AMD64 Archi‐
tecture Programmer's Manual.
SEE ALSO
isalist(1), getisax(2), sysinfo(2)
For information about the -xarch options supported by the C compiler,
see the Oracle Developer Studio 12.6: C User's Guide (https://docs.ora‐
cle.com/cd/E77782_01/html/E77788/bjapr.html#OSSCGbkaza).
NOTES
Instruction extensions to the native platform ABI are also represented
by hardware capabilities. For a complete description of hardware capa‐
bilities, refer to the Oracle Solaris 11.4 Linkers and Libraries Guide.
Oracle Solaris 11.4 4 May 2020 isalist(7)